A packaged integrated circuit device typically has one or more integrated circuit dies contained therein. Each integrated circuit die must be tested in its die form before packaging (typically called “wafer sort testing”). Wafer sort testing has two competing trade-offs. On one hand, it is desired to test all of the input/output pads. However, on the other hand, it is desirable to keep the test cost down, as well as to test the die rapidly.
One prior art solution is to test the die in wafer sort using only some of the input/output pads. Thereafter, during the final test, i.e. after the die is packaged, the other input/output pads, i.e. input/output pads not tested during wafer sort, are tested. Although, this method is fast and inexpensive, it could result in the case that defective dies are packaged, because those input/output pads that are not wafer sort tested cause a fault during final testing (i.e. after packaging). This results in the scraping of the packaged device. Scraping the packaged device is costly.
Another prior art solution is to test all of the input/output pads during wafer sort. Although, this solution is more expensive and time consuming, it will detect defective dies while still at the wafer sort stage, before the defective die is packaged.
Another complication is that in the packaging of MCP (Multi-chip Packaging), wherein a number of dies are packaged together in a single package, some input/output pads of a die may be used to connect to other dies, internal to the MCP and never be tested (or accessible to testing) after final MCP packaging.
Hence there is a need to solve the problem of wafer sort testing in an inexpensive and rapid manner, as well as the problem of testing put/output pads of a die that are internal to a MCP package.